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- W2078703397 abstract "MOS Current-Mode Logic (MCML) is usually used for high-speed applications. However, the large static power dissipation of MCML circuit limits its application in portable devices. In this work, we proposed a power-gating (PG) technique to reduce the standby power of the near-threshold MCML. The PG 1-bit full adder and a mod-10 counter are designed and simulated using HSPICE at 45nm CMOS technology with predictive technology model (PTM) model. The simulation results show that the standby power of the PG- adder and PG-counter is only 1.0nW and 3.0 nW, respectively. And the performance of the PG MCML circuits does not deteriorate. Keywords-lowe power; power-gating; current mode logic; near-threshold" @default.
- W2078703397 created "2016-06-24" @default.
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- W2078703397 date "2013-01-01" @default.
- W2078703397 modified "2023-10-16" @default.
- W2078703397 title "Low-Power Near-threshold MOS Current Mode Logic with Power-Gating Techniques" @default.
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- W2078703397 doi "https://doi.org/10.2991/iccsee.2013.424" @default.
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