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- W2079229908 abstract "An all-static CMOS 65nm SOI ADPLL has a fully programmable loop filter and a 3 <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>rd</sup> -order DeltaSigmamodulator. The DCO is a 3-stage, static-inverter-based ring-oscillator programmable in 768 frequency steps. The ADPLL locks from 500MHz to 8GHz at 1.3V 25degC, and 90MHz to 1.2GHz at 0.5V 100degC. The area is 200times150mum <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> and it dissipates 8mW/GHz at 1.2V and 1.6mW/GHz at 0.5V. The synthesized 4GHz clock has period jitter of 0.7ps <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>rms</sub> , and long-term jitter of 6ps <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>rms</sub> . The phase noise is -110dBc/Hz at 10MHz offset" @default.
- W2079229908 created "2016-06-24" @default.
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- W2079229908 date "2007-02-01" @default.
- W2079229908 modified "2023-10-15" @default.
- W2079229908 title "A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm SOI" @default.
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- W2079229908 doi "https://doi.org/10.1109/isscc.2007.373349" @default.
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