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- W2080266722 endingPage "2951" @default.
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- W2080266722 abstract "This paper presents a high-throughput decoder architecture for non-binary low-density parity-check (LDPC) codes, where the <i xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>q</i> -ary sum-product algorithm (QSPA) in the log domain is considered. We reformulate the check-node processing such that an efficient trellis-based implementation can be used, where forward and backward recursions are involved. In order to increase the decoding throughput, bidirectional forward-backward recursion is used. In addition, layered decoding is adopted to reduce the number of iterations based on a given performance. Finally, a message compression technique is used to reduce the storage requirements and hence the area. Using a 90-nm CMOS process, a 32-ary (837,726) LDPC decoder was implemented to demonstrate the proposed techniques and architecture. This decoder can achieve a throughput of 233.53 Mb/s at a clock frequency of 250 MHz based on the post-layout results. Compared to the decoders presented in previous literature, the proposed decoder can achieve the highest throughput based on a similar/better error-rate performance." @default.
- W2080266722 created "2016-06-24" @default.
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- W2080266722 date "2013-06-01" @default.
- W2080266722 modified "2023-10-14" @default.
- W2080266722 title "A High-Throughput Trellis-Based Layered Decoding Architecture for Non-Binary LDPC Codes Using Max-Log-QSPA" @default.
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- W2080266722 doi "https://doi.org/10.1109/tsp.2013.2256905" @default.
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