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- W2080456770 abstract "The multimedia capabilities of emerging high-end battery powered mobile devices rely on monolithic hardwareaccelerators with long latencies to minimize interrupt and software overheads. When compared to pure softwareimplementations, monolithic hardware accelerator solutions need an order of magnitude less power. However, they arerather inflexible and difficult to modify to provide support for multiple coding standards. A more flexible alternative isto employ finer grained short latency accelerators that implement the individual coding functions. Unfortunately, withthis approach the software overheads can become very high, if interrupts are used for synchronizing the software andhardware. Preferably, the cost of hardware accelerator interfacing should be at the same level with software functions. Inthis paper we study the benefits attainable from such an approach. As a case study we restructure a MPEG-4 videodecoder in a manner that enables the simultaneous decoding of multiple bit streams using short latency hardwareaccelerators. The approach takes multiple video bit streams as input and produces a multiplexed stream that is used tocontrol the hardware accelerators without interrupts. The decoding processes of each stream can be considered asthreads that share the same hardware resources. Software simulations predict that the energy efficiency of the approachwould be significantly better than for a pure software implementation." @default.
- W2080456770 created "2016-06-24" @default.
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- W2080456770 date "2007-02-15" @default.
- W2080456770 modified "2023-10-04" @default.
- W2080456770 title "Restructuring a software based MPEG-4 video decoder for short latency hardware acceleration" @default.
- W2080456770 doi "https://doi.org/10.1117/12.702333" @default.
- W2080456770 hasPublicationYear "2007" @default.
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