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• W2080586212 abstract "In nanoscale digital CMOS IC design, the large technology parameter variations have boosted the interest in statistical performance analysis. As the huge execution time of SPICE-based transistor-level Monte Carlo analysis is impractical for complex designs, there is a need for making accurate Monte Carlo analysis feasible through fast logic-level simulators. This paper presents a new, general logic model of digital CMOS cells featuring technology variation aware timing, and its prototype implementation in a standard hardware-description-language environment. The application of the approach to typical standard cells and test circuits shows very good agreement with SPICE BSIM4 transistor-level simulation both for nominal delay and for statistical Monte Carlo analyses." @default.
• W2080586212 created "2016-06-24" @default.
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• W2080586212 date "2014-06-01" @default.
• W2080586212 modified "2023-09-27" @default.
• W2080586212 title "Logic Drivers: A Propagation Delay Modeling Paradigm for Statistical Simulation of Standard Cell Designs" @default.
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• W2080586212 doi "https://doi.org/10.1109/tvlsi.2013.2269838" @default.
• W2080586212 hasPublicationYear "2014" @default.
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