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- W2080587764 abstract "This paper, focus on synthesis design of a Δ–Σ digital-to-analog converter (DAC) algorithm intended for professional digital audio. A rapid register-transfer-level (RTL) using a top-down design method with VHSIC hardware description language (VHDL) is practiced. All the RTL design simulation, VHDL implementation and field programmable gate array (FPGA) verification are rapidly and systematically performed through the methodology. A distributed pipelining, streaming and resource sharing design are considered for area and speed optimization while maintaining the original precision of the audio DAC. The features of the design are high-precision, fast processing and low-cost. The related work is done with the MATLAB & QUARTUS II simulators." @default.
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- W2080587764 date "2015-02-10" @default.
- W2080587764 modified "2023-09-25" @default.
- W2080587764 title "FPGA-Based Design Δ–Σ Audio D/A Converter with a Resolution Clock Generator Enhancement Circuit" @default.
- W2080587764 cites W118952169 @default.
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- W2080587764 doi "https://doi.org/10.1142/s0218126615500371" @default.
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