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• W2082421670 abstract "Latch circuits have advantage for timing and are widely used for high-speed custom circuits. However, ASIC design flows are based on the circuits with flip-flops. Then, ASIC designers don't use latches. This paper describes a new timing optimization algorithm for ASIC by replacing flip-flops to latches without changing the functionality of the circuits. After latch replacement, restricted retiming called fixed-phase retiming is carried out for timing optimization by minimizing the impact of clock skew and jitter. The experimental results show that 17% delay improvement of the benchmark circuits is achieved by proposed algorithms." @default.
• W2082421670 created "2016-06-24" @default.
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• W2082421670 date "2004-01-27" @default.
• W2082421670 modified "2023-09-27" @default.
• W2082421670 title "Timing optimization by replacing flip-flops to latches" @default.
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• W2082421670 doi "https://doi.org/10.5555/1015090.1015135" @default.
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