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- W2082661036 abstract "A LDPC decoder chip supporting four code rates of IEEE 802.15.3c applications is presented. The row-based layered scheduling with normalized min-sum algorithm is proposed to reduce the iteration number while maintaining similar performance. In addition, the reconfigurable 8/16/32-input sorter is designed to deal with four LDPC codes. In order to alleviate routing complexity, both of the reallocation of sorter inputs and pre-coding routing network are proposed to reduce the input numbers of multiplexers by 64%. Fabricated in 65-nm 1P10M CMOS process, this test chip can achieve maximum 5.79Gbps throughput for the highest code rate code while the hardware efficiency and energy efficiency are 3.7Gbps/mm2 and 62.4pJ/bit, respectively." @default.
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- W2082661036 date "2010-11-01" @default.
- W2082661036 modified "2023-09-27" @default.
- W2082661036 title "A 5.7Gbps row-based layered scheduling LDPC decoder for IEEE 802.15.3c applications" @default.
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- W2082661036 doi "https://doi.org/10.1109/asscc.2010.5716617" @default.
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