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- W2083981845 abstract "Density-prioritized memories such as NAND-ROM require a longer single-ended bitline (BL) sensing scheme to maintain high cell array efficiency and therefore suffer from a reduced BL sensing margin at ultra-low supply voltages (VDD) for read-0. This is the result of 1) reduced BL discharge driving current due to limited cell size and driving voltage; and 2) a larger BL false drop noise for read-1. This study proposes a data-aware sensing reference (DASR) scheme, capable of maintaining sensing margins for both read-0 and read-1 under given timing constraints. The key mechanism involved in maintaining the sensing margin is the adaptive changing of the reference voltage ( <i xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>VREF</i> ), such that the sensing headroom or potential range ( <i xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>VBL</i> - <i xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>VREF</i> ) for read-1 and read-0 overlap, as in differential BL sensing. Two 256 Kb DASR NAND-ROM macros, with and without code-inversion schemes, were fabricated using a 90 nm bulk CMOS logic process. The 256 Kb DASR NAND-ROM macros are functional down to 0.25 V. DASR also increases the access speed by 66.7% at 0.31 V VDD, compared with the conventional approach without the proposed DASR scheme." @default.
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- W2083981845 date "2013-02-01" @default.
- W2083981845 modified "2023-09-23" @default.
- W2083981845 title "Low-Voltage Embedded NAND-ROM Macros Using Data-Aware Sensing Reference Scheme for VDDmin, Speed and Power Improvement" @default.
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- W2083981845 doi "https://doi.org/10.1109/jssc.2012.2229068" @default.
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