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- W2084389705 abstract "A hardware technique for testing large programmable arrays is presented. The method is based on an appropriate circuit partitioning and on using nonlinear feedback shift registers for test pattern generation. It allows the testing of a PLA within a number of cycles that is a linear function of the number of inputs and product terms. A 8 times 16 times 8 PLA is completely tested within 52 cycles; a 16 times 48 times 8 PLA requires 132 cycles. The test patterns do not depend on the individual personalization of any PLA. So there is no more need of an extensive fault simulation or test pattern computation. The result is a fast efficient built-in test for PLA-macros, the most promising building blocks of VLSI circuits." @default.
- W2084389705 created "2016-06-24" @default.
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- W2084389705 date "1981-11-01" @default.
- W2084389705 modified "2023-09-27" @default.
- W2084389705 title "A hardware approach to self-testing of large programmable logic arrays" @default.
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- W2084389705 doi "https://doi.org/10.1109/tcs.1981.1084933" @default.
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