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- W2084602893 abstract "Wavelets have widely been used in many signal and image processing applications. In this paper, a new serial-parallel architecture for wavelet-based image compression is introduced. It is based on a 4-tap wavelet transform, which is realised using some FIFO memory modules implementing a pixel-level pipeline architecture to compress and decompress images. The real filter calculation over 4x4 window blocks is done using a tree of carry save adders to ensure the high speed processing required for many applications. The details of implementing both compressor and decompressor sub-systems are given. The primarily analysis reveals that the proposed architecture, implemented using current VLSI technologies, can process a video stream in real time." @default.
- W2084602893 created "2016-06-24" @default.
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- W2084602893 date "2005-11-01" @default.
- W2084602893 modified "2023-10-14" @default.
- W2084602893 title "Design and performance of a pixel-level pipelined-parallel architecture for high speed wavelet-based image compression" @default.
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- W2084602893 doi "https://doi.org/10.1016/j.compeleceng.2005.07.005" @default.
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