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- W2085247198 abstract "With the advent of new services and capabilities for the next generation of mobile communication systems, new powerful error-correcting schemes have emerged as an effective way to increase cellular capacity and achieve higher transmission data rates. A new set of Error-Correcting Codes (ECCs) called Low-Density Parity Check Codes (LDPCs) have recently reemerged which significantly reduce error-rates compared to conventional ECCs. This coding scheme, similarly to other coding techniques like Turbo Codes, achieve near-Shannon capacity, but unlike Turbo Codes, they offer great possibilities for implementation and parallelisation in reconfigurable systems such as Field Programmable Gate Arrays (FPGA). FPGA technology offers devices with a large scale of integration. However, during the process of logic synthesis, there is a stage called technology mapping, which is considered not to be optimal enough. In this paper, it will be shown that the use of Evolutionary Algorithms and particularly Genetic Algorithms are especially suitable for the optimisation of the technology mapping process. These algorithms model natural evolution processes using selection, crossover and mutation operations and significantly optimise the routing delay in the mapping process compared to comercial automatic mapping tools. A methodology for the implementation of an LDPC encoder/decoder in a commercial FPGA and a Genetic Algorithm that is used to optimise this implementation will be presented. The proposed scheme highlights the potential of evolutionary methods in the reconfigurability of wireless devices." @default.
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- W2085247198 date "2002-01-01" @default.
- W2085247198 modified "2023-09-26" @default.
- W2085247198 title "On the implementation and optimisation of LDPC codes on a reconfigurable hardware for future communications systems" @default.
- W2085247198 doi "https://doi.org/10.1049/cp:20020388" @default.
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