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- W2085263487 abstract "This report describe the hardware architecture and software implementation of a hologram computing system developed at the MIT Media Laboratory. The hologram computing employs specialized stream-processing hardware embedded in the Cheops Image Processing system--a compact, block data-flow parallel processor. A superposition stream processor performs weighted summations of arbitrary 1D basis functions. A two-step holographic computation method--called Hogel-Vector encoding--utilizes the stream processor's computational power. An array of encoded hogel vectors, generated from a 3D scene description, is rapidly decoded using the processor. The resulting 36-megabyte holographic pattern is transferred to frame- buffers and then fed to a real-time electro-holographic display, producing 3D holographic images. System performance is sufficient to generate an image volume approximately 100 mm per side in 3 seconds. The architecture is scalable over a limited range in both display size and computational power. The limitations on system scalability will be identified and solutions proposed." @default.
- W2085263487 created "2016-06-24" @default.
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- W2085263487 date "1995-04-12" @default.
- W2085263487 modified "2023-10-16" @default.
- W2085263487 title "<title>Hardware architecture for rapid generation of electro-holographic fringe patterns</title>" @default.
- W2085263487 doi "https://doi.org/10.1117/12.206216" @default.
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