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• W2085320420 abstract "A 3-D test circuit examining thermal propagation within a through-silicon via-based 3-D integrated stack has been designed, fabricated, and tested. Design insight into thermal coupling in 3-D integrated circuits (ICs) through both experiment and simulation is provided, and suggestions to mitigate thermal effects in 3-D ICs are offered. Two wafers are vertically bonded to form a 3-D stack. Intraplane and interplane thermal coupling is investigated through single-point heat generation using resistive thermal heaters and temperature monitoring through four-point resistive measurements. Thermal paths are identified and analyzed based on the metric of thermal resistance per unit length. The peak steady-state temperature due to die location within a 3-D stack is described. The reduction in peak temperature through fan-based active cooling is also reported. Thermal propagation from a heat source located on the backside of the silicon is examined with both back metal and on-chip thermal sensors. A comparison of thermal coupling between two different heat sources on the same device plane is also provided." @default.
• W2085320420 created "2016-06-24" @default.
• W2085320420 creator A5053517349 @default.
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• W2085320420 date "2015-10-01" @default.
• W2085320420 modified "2023-09-27" @default.
• W2085320420 title "Experimental Analysis of Thermal Coupling in 3-D Integrated Circuits" @default.
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• W2085320420 doi "https://doi.org/10.1109/tvlsi.2014.2357441" @default.
• W2085320420 hasPublicationYear "2015" @default.
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