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- W2086146621 abstract "A fully-digital capacitive sensor readout circuit based on capacitance controlled oscillators is presented. A two-step quantization scheme using SAR for coarse conversion and ΔΣ for fine conversion is introduced to extend the sensor input range while preserving the sensing accuracy. Systematic error analysis and optimization for the finite switch on-resistance and buffer input dependent delay are also outlined. Power supply insensitivity is ensured by the use of a pseudo-differential architecture and a ratiometric readout scheme. The complete sensor readout is implemented in a standard 0.18μm CMOS process. Simulation results show that the sensor readout circuit can achieve a wide input range from 1.5 to 6.5pF and a worst case power supply rejection ratio of 0.65% from 0.3V to 0.6V. For the ΔΣ conversion, a resolution of 7.4b at a conversion frequency of 318 Hz with an input capacitance of 4pF and a 0.3V supply is achieved. An average power is 37.5nW at 0.3V with a 4pF input capacitance, corresponding to a Figure-of-Merit (FoM) of 350fJ/conv-step." @default.
- W2086146621 created "2016-06-24" @default.
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- W2086146621 date "2014-12-01" @default.
- W2086146621 modified "2023-10-01" @default.
- W2086146621 title "A 0.3-V, 37.5-nW 1.5∼6.5-pF-input-range supply voltage tolerant capacitive sensor readout" @default.
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- W2086146621 doi "https://doi.org/10.1109/isicir.2014.7029516" @default.
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