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• W2087046223 abstract "Low-frequency noise is used to study the electronic transport in arrays of 14 nm gate length vertical silicon nanowire devices. We demonstrate that, even at such scaling, the electrostatic control of the gate-all-around is sufficient in the sub-threshold voltage region to confine charges in the heart of the wire, and the extremely low noise level is comparable to that of high quality epitaxial layers. Although contact noise can already be a source of poor transistor operation above threshold voltage for few nanowires, nanowire parallelization drastically reduces its impact." @default.
• W2087046223 created "2016-06-24" @default.
• W2087046223 creator A5000731938 @default.
• W2087046223 creator A5039115636 @default.
• W2087046223 date "2013-12-23" @default.
• W2087046223 modified "2023-10-05" @default.
• W2087046223 title "Electronic transport mechanisms in scaled gate-all-around silicon nanowire transistor arrays" @default.
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• W2087046223 doi "https://doi.org/10.1063/1.4858955" @default.
• W2087046223 hasPublicationYear "2013" @default.
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