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• W2087825164 abstract "Popular generic fault models, which exhibit limited realism for different IC technologies, have been widely misused due to their simplicity and cost-effective implementation. This paper introduces a system for deriving accurate, technology specific fault models that are based on analog defect simulation. This technique, though used in other research efforts, is formally defined in this paper and a systematic approach is developed. It is supported by a new software tool that provides a push-button solution for the previously tedious task of obtaining accurate ASIC cell defect to fault mappings. Furthermore, upon completion of the cell defect analysis, the tool automatically generates VITAL compliant, defect-injectable, VHDL cell models." @default.
• W2087825164 created "2016-06-24" @default.
• W2087825164 creator A5002571587 @default.
• W2087825164 creator A5017920414 @default.
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• W2087825164 date "2006-07-01" @default.
• W2087825164 modified "2023-09-27" @default.
• W2087825164 title "Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries" @default.
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• W2087825164 doi "https://doi.org/10.1016/j.vlsi.2005.08.002" @default.
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