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• W2088271196 abstract "Abstract A low power output-capacitor-free low-dropout (LDO) regulator, with subthreshold slew-rate enhancement technique, has been proposed and simulated using a standard 0.18 μm CMOS process in this paper. By utilizing such a technique, proposed LDO is able to achieve a fast transient response. Simulation results verify that the recovery time is as short as 7 μs and the maximum undershoot and overshoot are as low as 55 mV and 30 mV, respectively. In addition, the slew-rate enhancement circuit works in the subthreshold region at steady state, and proposed LDO consumes a 46.4-μA quiescent current to provide a maximum 100-mA load with a minimum 0.2-V dropout voltage. Besides, excellent line and load regulations are obtained and the values are 0.37 mV/V and 2 μV/mA, respectively." @default.
• W2088271196 created "2016-06-24" @default.
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• W2088271196 date "2014-06-01" @default.
• W2088271196 modified "2023-09-22" @default.
• W2088271196 title "An output-capacitor-free low-dropout regulator with subthreshold slew-rate enhancement technique" @default.
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• W2088271196 doi "https://doi.org/10.1016/j.mejo.2014.04.012" @default.
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