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• W2088941036 abstract "Jitter limitations pose significant challenges for high-resolution and sampling-rate analog-to-digital converters (ADCs). This paper describes an integrate-and-sample (IAS) receiver suitable for use in an optical parametric photonic ADC. Rate-scalable photonic-sampling techniques provide low-jitter optical sampling and analog-to-digital conversion of the wideband signal up to 10 GHz and beyond. An 8-bit 2-GS/s IAS receive channel is described for a rate-scalable photonic ADC. Electronic measurements are shown for an RF tone and a photonic Gaussian pulse source and compared to simulations. A two-channel IAS array is fabricated in a 120-nm SiGe BiCMOS process and packaged onto a printed circuit board for integration into the photonic-sampling setup. A single 2-GS/s channel achieves a measured performance higher than 8.1 ENOB. The two-channel integrated circuit consumes 890 mA per channel from 5- and 2.5-V supplies and occupies an area of 1.6 × 2.0 mm2." @default.
• W2088941036 created "2016-06-24" @default.
• W2088941036 creator A5024558404 @default.
• W2088941036 creator A5053636136 @default.
• W2088941036 date "2012-12-01" @default.
• W2088941036 modified "2023-09-26" @default.
• W2088941036 title "An 8-bit Integrate-and-Sample Receiver for Rate-Scalable Photonic Analog-to-Digital Conversion" @default.
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• W2088941036 doi "https://doi.org/10.1109/tmtt.2012.2222042" @default.
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