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- W2088983172 abstract "This paper uses a 3-bit ADC to blindly sample the received data at 3× the baud rate to recover the data. By moving from 2× to 3× sampling, we reduce the required ADC resolution from 5-bit to 3-bit, thereby reducing the overall power consumption by a factor of 2. Measurements from our fabricated test chip in Fujitsu's 65nm CMOS show a high frequency jitter tolerance of 0.19UIpp for a 5Gbps PRBS31 with a 16 FR4 channel." @default.
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- W2088983172 date "2013-11-01" @default.
- W2088983172 modified "2023-09-26" @default.
- W2088983172 title "A 3x blind ADC-based CDR" @default.
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- W2088983172 doi "https://doi.org/10.1109/asscc.2013.6691054" @default.
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