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- W2089136983 abstract "This work presents a memory hierarchy model for a full search motion estimation core. The motion estimation is the most complex module in a video encoder requiring intensive computation and high memory bandwidth, mainly when the focus is high definition videos. The proposed memory hierarchy model is based on a data reuse scheme considering the full search algorithm features. The proposed memory hierarchy expressively reduces the external memory bandwidth required for the motion estimation process and it provides a very high data throughput for the ME core. This throughput is necessary to achieve real time when processing high definition videos. When considering the worst bandwidth scenario, this memory hierarchy is able to reduce the external memory bandwidth in 578 times. A case study for the proposed hierarchy, using 32x32 search window and 8x8 block size, was implemented and prototyped on a Virtex 4 FPGA. The results show that is possible to reach 38 frames per second when processing Full HD frames (1920x1080 pixels) using nearly 299Mbytes per second of external memory bandwidth." @default.
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- W2089136983 date "2011-08-30" @default.
- W2089136983 modified "2023-10-14" @default.
- W2089136983 title "An efficient memory hierarchy for full search motion estimation on high definition digital videos" @default.
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- W2089136983 doi "https://doi.org/10.1145/2020876.2020907" @default.
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