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- W2089463003 abstract "Modulo 2n+1 multiplier is one of the critical components in the area of digital signal processing, residue arithmetic, and data encryption that demand high-speed and low-power operation. In this paper, a new circuit implementation of a high-speed low-power modulo 2n+1 multiplier is proposed. It has three major stages: partial product generation stage, partial product reduction stage, and the final adder stage. The proposed structure introduces a new MUX-based compressor in the partial product reduction stage to reduce power and increase speed, and in the final adder stage, the Sparse-tree-based inverted end-around-carry adder reduces the number of critical path circuit blocks, also avoids wire interconnection problem. The proposed multiplier is implemented using both 32nm CNTFET (Carbon-Nanotube FET) and bulk CMOS technology for performance comparison. The CNTFET-based design dramatically decreases the PDP (Power Delay Product) of the circuit. The simulation results demonstrate that the power consumption of CNTFET-based multiplier is at average 5.72 times less than its CMOS counterpart, while the PDP of CNTFET is 94 times less than the CMOS one." @default.
- W2089463003 created "2016-06-24" @default.
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- W2089463003 date "2012-08-01" @default.
- W2089463003 modified "2023-10-16" @default.
- W2089463003 title "A high speed low power modulo 2<sup>n</sup>+1 multiplier design using carbon-nanotube technology" @default.
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- W2089463003 doi "https://doi.org/10.1109/mwscas.2012.6292043" @default.
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