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- W2089729293 abstract "This paper presents a novel dynamically reconfigurable active L1 cache model for hybrid prototyping, called DRAC. The hybrid prototyping technique simulates a multicore embedded system using an emulation kernel on top of a single physical instance of a core. We extend hybrid prototyping by supporting memory hierarchy modeling with DRAC. The presented cache model is a standalone cycle accurate model that is further customized for multicore emulation. DRAC run-time configurability enables the embedded system designer to simulate and explore different multicore design options without the need for full FPGA prototyping. Our experimental results show 2.78% average error and 5.06% worst case error when DRAC is used as a standalone cache model in a single core design. We also observed 100% relative accuracy and less than 13% absolute worst case error in timing estimation when DRAC is used for hybrid prototyping of multicore designs." @default.
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- W2089729293 date "2014-10-01" @default.
- W2089729293 modified "2023-09-27" @default.
- W2089729293 title "DRAC: a dynamically reconfigurable active L1 cache model for hybrid prototyping of multicore embedded systems" @default.
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- W2089729293 doi "https://doi.org/10.1109/rsp.2014.6966897" @default.
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