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- W2090963250 abstract "As platform integration continues, different modules, including CPU, graphics, I/O interface, wireless transceivers and the power management unit, operate at different frequencies as shown in Fig. 3.8.1. In addition, maximizing battery life requires localized dynamic voltage frequency scaling (DVFS) and sleep mode support leading to independent clock domains for various functional unit blocks (FUBs). Also, clock generation units should be able to go to sleep and wake up rapidly to conserve power. Generating multiple clock signals while minimizing skews at the module interfaces is challenging. Furthermore, some modules require spread spectrum clocking (SSC), with different modulation patterns to avoid EMI, but yet such spreading is forbidden in modules requiring frequency accuracy (e.g. display interfaces). Diverse SSC generation requirements necessitate multiple reference clocks, extra pins, and off-chip components. With analog integer-n PLL-based clock generators, it is difficult to meet all these needs with a common reference clock. One disadvantage is that the frequency resolution in an integer-n PLL is limited by the reference frequency. A lower reference frequency limits the bandwidth and lock time, amplifies jitter from the reference, and increases the loop filter area. Additionally, analog PLLs suffer from unpredictable loop dynamics and clock skews with PVT, mismatch, and transistor leakage, further exacerbated by process scaling. Turning off and waking up an analog PLL requires charging or discharging loop filter capacitors which is inherently slow. This paper presents an all-digital clock generation architecture which (1) provides fractional-n capability in the digital domain; (2) implements SSC within the PLL loop; (3) performs digital clock deskew; and (4) provides dynamic loop bandwidth adjustment to shorten lock time." @default.
- W2090963250 created "2016-06-24" @default.
- W2090963250 creator A5002626327 @default.
- W2090963250 creator A5030341486 @default.
- W2090963250 creator A5036573077 @default.
- W2090963250 creator A5040812058 @default.
- W2090963250 creator A5058466731 @default.
- W2090963250 creator A5062357544 @default.
- W2090963250 date "2012-02-01" @default.
- W2090963250 modified "2023-09-26" @default.
- W2090963250 title "A reconfigurable distributed all-digital clock generator core with SSC and skew correction in 22nm high-k tri-gate LP CMOS" @default.
- W2090963250 cites W2082715750 @default.
- W2090963250 cites W2151340196 @default.
- W2090963250 cites W2164587179 @default.
- W2090963250 doi "https://doi.org/10.1109/isscc.2012.6176934" @default.
- W2090963250 hasPublicationYear "2012" @default.
- W2090963250 type Work @default.
- W2090963250 sameAs 2090963250 @default.
- W2090963250 citedByCount "12" @default.
- W2090963250 countsByYear W20909632502012 @default.
- W2090963250 countsByYear W20909632502013 @default.
- W2090963250 countsByYear W20909632502014 @default.
- W2090963250 countsByYear W20909632502015 @default.
- W2090963250 countsByYear W20909632502016 @default.
- W2090963250 countsByYear W20909632502017 @default.
- W2090963250 countsByYear W20909632502020 @default.
- W2090963250 crossrefType "proceedings-article" @default.
- W2090963250 hasAuthorship W2090963250A5002626327 @default.
- W2090963250 hasAuthorship W2090963250A5030341486 @default.
- W2090963250 hasAuthorship W2090963250A5036573077 @default.
- W2090963250 hasAuthorship W2090963250A5040812058 @default.
- W2090963250 hasAuthorship W2090963250A5058466731 @default.
- W2090963250 hasAuthorship W2090963250A5062357544 @default.
- W2090963250 hasConcept C113074038 @default.
- W2090963250 hasConcept C125576049 @default.
- W2090963250 hasConcept C12707504 @default.
- W2090963250 hasConcept C127204226 @default.
- W2090963250 hasConcept C127413603 @default.
- W2090963250 hasConcept C134652429 @default.
- W2090963250 hasConcept C137059387 @default.
- W2090963250 hasConcept C178693496 @default.
- W2090963250 hasConcept C22716491 @default.
- W2090963250 hasConcept C24326235 @default.
- W2090963250 hasConcept C2778023540 @default.
- W2090963250 hasConcept C41008148 @default.
- W2090963250 hasConcept C42196554 @default.
- W2090963250 hasConcept C46362747 @default.
- W2090963250 hasConcept C60501442 @default.
- W2090963250 hasConceptScore W2090963250C113074038 @default.
- W2090963250 hasConceptScore W2090963250C125576049 @default.
- W2090963250 hasConceptScore W2090963250C12707504 @default.
- W2090963250 hasConceptScore W2090963250C127204226 @default.
- W2090963250 hasConceptScore W2090963250C127413603 @default.
- W2090963250 hasConceptScore W2090963250C134652429 @default.
- W2090963250 hasConceptScore W2090963250C137059387 @default.
- W2090963250 hasConceptScore W2090963250C178693496 @default.
- W2090963250 hasConceptScore W2090963250C22716491 @default.
- W2090963250 hasConceptScore W2090963250C24326235 @default.
- W2090963250 hasConceptScore W2090963250C2778023540 @default.
- W2090963250 hasConceptScore W2090963250C41008148 @default.
- W2090963250 hasConceptScore W2090963250C42196554 @default.
- W2090963250 hasConceptScore W2090963250C46362747 @default.
- W2090963250 hasConceptScore W2090963250C60501442 @default.
- W2090963250 hasLocation W20909632501 @default.
- W2090963250 hasOpenAccess W2090963250 @default.
- W2090963250 hasPrimaryLocation W20909632501 @default.
- W2090963250 hasRelatedWork W1507223651 @default.
- W2090963250 hasRelatedWork W1537200032 @default.
- W2090963250 hasRelatedWork W2027411961 @default.
- W2090963250 hasRelatedWork W2090213929 @default.
- W2090963250 hasRelatedWork W2105005155 @default.
- W2090963250 hasRelatedWork W2110902574 @default.
- W2090963250 hasRelatedWork W2161776375 @default.
- W2090963250 hasRelatedWork W2186776886 @default.
- W2090963250 hasRelatedWork W2188936373 @default.
- W2090963250 hasRelatedWork W2210438891 @default.
- W2090963250 hasRelatedWork W2346441944 @default.
- W2090963250 hasRelatedWork W2485521470 @default.
- W2090963250 hasRelatedWork W2575732409 @default.
- W2090963250 hasRelatedWork W2617666058 @default.
- W2090963250 hasRelatedWork W2909835564 @default.
- W2090963250 hasRelatedWork W2821573841 @default.
- W2090963250 hasRelatedWork W2864932621 @default.
- W2090963250 hasRelatedWork W2926187747 @default.
- W2090963250 hasRelatedWork W3064322069 @default.
- W2090963250 hasRelatedWork W3067034444 @default.
- W2090963250 isParatext "false" @default.
- W2090963250 isRetracted "false" @default.
- W2090963250 magId "2090963250" @default.
- W2090963250 workType "article" @default.