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• W2091293296 abstract "In CMOS multistage clock buffer design, the duty-cycle of clock is liable to be changed when the clock passes through several buffer stages. The pulse-width may be changed due to unbalance of the p- and n-OS transistors in the long buffer. This paper describes a delay locked loop with double edge synchronization for use in a clock alignment process. Results of its SPICE simulation, that relate to 1.2 μm CMOS technology, shown that the duty-cycle of the multistage output pulses can be precisely adjusted to (50 ± 1)% within the operating frequency range, from 55 MHz up to 166 MHz." @default.
• W2091293296 created "2016-06-24" @default.
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• W2091293296 date "2008-01-01" @default.
• W2091293296 modified "2023-09-25" @default.
• W2091293296 title "Clock aligner based on delay locked loop with double edge synchronization" @default.
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• W2091293296 doi "https://doi.org/10.1016/j.microrel.2007.02.025" @default.
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