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- W2092082008 abstract "Hostile environments, shrinking feature sizes and processor aging elicit a need for resilient computing. Coarse-grained hardware approaches, such as Triple Modular Redundancy (TMR) and Temporal Redundancy (TR), while exhibiting acceptable levels of fault coverage [1], are often wasteful of resources such as time, device/chip area and power. A TMR-hardened computation can exhibit poor performance relative to a non-TMR hardware configuration with similar area. This is because the resources that are used to replicate functional units in parallel (in the case of TMR) can only execute one operation at a time. Conversely, in an equivalent non-TMR configuration, those same resources could execute three different operations concurrently (albeit with no resiliency coverage). In short, TMR is very rigid in its allocation of resources, using them only for resiliency." @default.
- W2092082008 created "2016-06-24" @default.
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- W2092082008 date "2012-08-01" @default.
- W2092082008 modified "2023-09-25" @default.
- W2092082008 title "A resiliency-aware scheduling approach for FPGA configuration: Preliminary results" @default.
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- W2092082008 doi "https://doi.org/10.1109/fpl.2012.6339196" @default.
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