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• W2093289146 abstract "In this paper we present a method for disparity map computing and its correspondent high parallel hardware accelerator. Our solution considers a two step processing algorithm. First, we compute a one-dimensional biased sum of absolute differences, and later a spurious removal technique is performed to eliminate wrong estimations. The hardware accelerator introduces a memory organization, an address generation scheme and data-path units that have scalable features for several resolutions, frame rates, silicon use, and power consumption instantiations. We have implemented a five stage pipelined organization that operates at 174.5 MHz over an VIRTEX II PRO 2vp30fg676-7 FPGA device, carries out an equivalent of 9.074 GOPS and processes 142 frames per second of Common Intermediate Format (CIF)." @default.
• W2093289146 created "2016-06-24" @default.
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• W2093289146 date "2010-07-01" @default.
• W2093289146 modified "2023-10-18" @default.
• W2093289146 title "High parallel disparity map computing on FPGA" @default.
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• W2093289146 doi "https://doi.org/10.1109/mesa.2010.5552049" @default.
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