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- W2093352503 abstract "Memory interleaving and multiple access ports are the key to a high memory bandwidth in vector processor systems. Each of the active ports supports an independent access stream to memory among which access conflicts may arise. Such conflicts lead to a decrease in memory bandwidth. The authors present some analytical results for the calculation of the resulting effect bandwidth for one and two access streams to a memory system in a vector processor. In particular, conditions for conflict-free access are given together with some conflicting cases that should be avoided. Finally, examples of measurements on a Cray X-MP and corresponding simulations are presented." @default.
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- W2093352503 date "1985-10-01" @default.
- W2093352503 modified "2023-10-17" @default.
- W2093352503 title "On the effective bandwidth of interleaved memories in vector processor systems" @default.
- W2093352503 doi "https://doi.org/10.1109/tc.1985.6312199" @default.
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