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• W2093581033 abstract "This paper presents a 2-D temperature-dependent analytical drain current model, which is valid for six different device architectures (by slightly modifying the used parameters), i.e., dual material gate dielectric pocket silicon-on-void, dual material gate silicon-on-void, dual material gate silicon-on-insulator, dielectric pocket silicon-on-void, silicon-on-void, and silicon-on-insulator MOSFETs. The results thus obtained, i.e., drain current, transconductance, g <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>m</sub> /I <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>ds</sub> ratio, threshold voltage, subthreshold slope, and I <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>on</sub> /I <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>off</sub> ratio have been verified with the simulated results obtained using ATLAS 3-D device simulator for channel length down to 30 nm. The analytical model is also used to investigate the impact of temperature variation on the characteristics of N-MOS inverter based on different architectures. In addition, impact of process and parameters variation (i.e., variation in shallow extension depth (X <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>e</sub> ), side pillar thickness (T <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>st</sub> ), thickness of buried oxide layer (t <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>3</sub> ) along with the variation in temperature) on the subthreshold performance of different devices has also been studied through exhaustive device simulation." @default.
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• W2093581033 date "2014-07-01" @default.
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• W2093581033 title "Investigation of Electrostatic Integrity of Nanoscale Dual Material Gate Dielectric Pocket Silicon-on-Void (DMGDPSOV) MOSFET for Improved Device Scalability" @default.
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• W2093581033 doi "https://doi.org/10.1109/tnano.2014.2314146" @default.
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