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• W2094381567 abstract "Power consumption has become the major factor that has to be considered while designing systems using reconfigurable devices, especially for battery-operated applications. Minimizing transitions is one of the ways to reduce power consumption. Overwriting a register with the same value occurs frequently in real digital systems. Such unneeded transitions increase the power consumption. To avoid this, a new HDL coding style to reduce power consumption for reconfigurable devices is proposed. The idea is to “force” the CAD tool to configure the CLB flip-flop as a T flip-flop with its T input held constantly at logic one and drive its clock through the lookup table(LUT). Based on an extensive evaluation using MCNC benchmark circuits on a real FPGA and a real CAD tool, our proposal reduces total power consumption by 13-90 % and runs 2-20 % faster with 0-45 % area overhead compared to conventional coding style solutions. As a parallel activity we proposed a new logic element (LE) that implements the proposed design style directly." @default.
• W2094381567 created "2016-06-24" @default.
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• W2094381567 date "2010-12-01" @default.
• W2094381567 modified "2023-09-27" @default.
• W2094381567 title "A novel HDL coding style to reduce power consumption for reconfigurable devices" @default.
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• W2094381567 doi "https://doi.org/10.1109/fpt.2010.5681480" @default.
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