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- W2094908973 abstract "Over the last five years, major microprocessor manufacturers have released plans for a rapidly increasing number of cores per microprossesor, with upwards of 64 cores by 2015. In this setting, a sequential RAM computer will no longer accurately reflect the architecture on which algorithms are being executed. In this paper we propose a model of low degree parallelism (LoPRAM) which builds upon the RAM and PRAM models yet better reflects recent advances in parallel (multi-core) architectures. This model supports a high level of abstraction that simplifies the design and analysis of parallel programs. More importantly we show that in many instances it naturally leads to work-optimal parallel algorithms via simple modifications to sequential algorithms." @default.
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- W2094908973 date "2008-01-01" @default.
- W2094908973 modified "2023-10-18" @default.
- W2094908973 title "Optimal speedup on a low-degree multi-core parallel architecture (LoPRAM)" @default.
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- W2094908973 doi "https://doi.org/10.1145/1378533.1378568" @default.
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