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• W2095603303 abstract "This paper investigates the design of low-voltage low-power switched-capacitor (SC) filters for high-frequency applications by using the clock-booster approach. In particular, our proposed SC filter architecture uses single-ended double-sampling integrator cells based on low-voltage operational transconductance amplifiers which take advantage of dynamic biasing and the clock-booster technique to drive the switch transistors. To validate its high-frequency capability, two low-pass elliptic SC filters respectively with a corner frequency of 6 and 8-MHz, were designed in a 0.35-/spl mu/m CMOS process. Both are suitable for telecom applications and can operate with a power supply as low as 1.5 V, while dissipating 11 mW. Measurements showed that for an output amplitude of 1 V/sub pp/, their total harmonic distortions were maintained well below -40 dB in their bandwidths. Comparisons with other SC filter implementations in the literature, which highlight the quality of our implementation are also provided." @default.
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• W2095603303 date "2004-02-01" @default.
• W2095603303 modified "2023-10-13" @default.
• W2095603303 title "Exploiting the high-frequency performance of low-voltage low-power SC filters" @default.
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• W2095603303 doi "https://doi.org/10.1109/tcsii.2003.821525" @default.
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