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- W2095657515 abstract "In this paper, we present a bit-serial systolic architecture for computation of the discrete wavelet transform (DWT). The computations pertaining to the low-pass and high-pass filters of the recursive pyramid algorithm (RPA) are computed separately by two different layers in the proposed bi-layer structure. The structure is fully pipelined and requires a clocking period of only one full-adder delay. The hardware complexity of the proposed design is 58% of the existing bit-serial architecture up to 4-th level of decomposition with less than half of the computation time of the other" @default.
- W2095657515 created "2016-06-24" @default.
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- W2095657515 date "2006-01-01" @default.
- W2095657515 modified "2023-09-26" @default.
- W2095657515 title "Bi-Layer Systolic Architecture for Bit-Serial Implementation of Discrete Wavelet Transform" @default.
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- W2095657515 doi "https://doi.org/10.1109/iccs.2006.301395" @default.
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