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• W2095913060 abstract "<para xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink> Aggressively scaling the supply voltage of SRAMs greatly minimizes their active and leakage power, a dominating portion of the total power in modern ICs. Hence, energy constrained applications, where performance requirements are secondary, benefit significantly from an SRAM that offers read and write functionality at the lowest possible voltage. However, bit-cells and architectures achieving very high density conventionally fail to operate at low voltages. This paper describes a high density SRAM in 65 nm CMOS that uses an 8T bit-cell to achieve a minimum operating voltage of 350 mV. Buffered read is used to ensure read stability, and peripheral control of both the bit-cell supply voltage and the read-buffer's foot voltage enable sub-<formula formulatype=inline> <tex>$V_{t}$</tex></formula> write and read without degrading the bit-cell's density. The plaguing area-offset tradeoff in modern sense-amplifiers is alleviated using redundancy, which reduces read errors by a factor of five compared to device up-sizing. At its lowest operating voltage, the entire 256 kb SRAM consumes 2.2 <formula formulatype=inline><tex>$mu$</tex></formula>W in leakage power. </para>" @default.
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• W2095913060 date "2008-01-01" @default.
• W2095913060 modified "2023-10-13" @default.
• W2095913060 title "A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy" @default.
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• W2095913060 doi "https://doi.org/10.1109/jssc.2007.908005" @default.
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