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- W2095971323 abstract "While fauli models for various implementaiions of combinaiional logic have been examined in deiail, only limited attention has been paid io storage eletuenis. In many designs, siorage elements (SEs) represent a significant fraction of the electrical nodes. Mosi iesiable designs are geared towards testing of combinational logic, and generally depend on an increase in nuinber of SEs. The stuck-at fault model assuiiies that an output (input) of a SE can be stuck-ai-0 or 1. This minimal fauli model may not model some comiiion fauli behaviors for SEs. These include feed-through faulls which cause ilre cell to erhibii data or clockfeed-through behavior, and ihe inabiliiy io laic11 H or L signals. In a master-slave cell, or when two-phase clocking is used, many of these faults may appear as output .duck-at faults. The miniiiral fault model may be an efficient fault model when only modest coverage may be required. The enhanced fault model pro" @default.
- W2095971323 created "2016-06-24" @default.
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- W2095971323 date "2005-08-24" @default.
- W2095971323 modified "2023-09-27" @default.
- W2095971323 title "Use of Storage Elements as Primitives for Modeling Faults in Synchronous Sequential Circuits" @default.
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- W2095971323 doi "https://doi.org/10.1109/icvd.1993.669660" @default.
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