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- W2096951038 abstract "Stacked-gate memory devices have been realized which for the first time demonstrate efficient hot carrier writing for drain-source bias, V/sub DS/, down to 2.5 V. Writing is achieved by channel initiated secondary electron injection, which permits writing for qV/sub DS/ below the 3.2 eV oxide barrier. Writing times of 1 ms are achieved for floating gate voltages V/sub FG/ as low as 1.2 V, with V/sub DS/=-V/sub BS/=2.5 V, voltages which can easily be derived from a single scaled power supply, the back-gate bias generated by low-current charge pumping. No high voltage transistors are required for writing or V/sub T/ convergence. Moreover, because the devices are based on a fully scaled 0.25 /spl mu/m CMOS process, NV-memory arrays can be easily integrated with a minimum of additional process steps. Tight V/sub T/ convergence together with low voltage operation and scaling compatibility makes them ideal candidates for Giga-bit Flash." @default.
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- W2096951038 date "2002-11-19" @default.
- W2096951038 modified "2023-10-14" @default.
- W2096951038 title "EEPROM/flash sub 3.0 V drain-source bias hot carrier writing" @default.
- W2096951038 cites W1761051592 @default.
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- W2096951038 doi "https://doi.org/10.1109/iedm.1995.499382" @default.
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