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• W2097223010 abstract "In this paper, we present a new VLSI architecture for a low-power turbo decoder. First, we develop a new soft-in-soft-out decoder architecture and change the sliding window operating flow without attaching LIFO memory. Moreover, we propose a new stopping iteration algorithm that integrates two stop criteria to avoid unnecessary iterations, especially in low SNR channels. Experiments show that our architecture gets 25.3%/spl sim/39.8% memory size saving in our SISO decoder architecture and one window saving of decoding delay in comparison with the traditional decoder." @default.
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• W2097223010 date "2005-07-27" @default.
• W2097223010 modified "2023-09-25" @default.
• W2097223010 title "A New Low-power Turbo Decoder Using HDA-DHDD Stopping Iteration" @default.
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• W2097223010 doi "https://doi.org/10.1109/iscas.2005.1464769" @default.
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