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- W2097323304 abstract "SRAM compiler uses predefined building blocks or leaf cells and connectivity information to compile SRAMs of user-specified size. In this paper, a high-speed embedded SRAM compiler is described. It is based on TSMC's 0.5 /spl mu/m CMOS process. It can compile both single-port and dual-port SRAMs. SRAM is a completely synchronous architecture with a maximal capacity 16k/spl times/64=1 Mb bits. The compiler generates the layout, behavioral level models, schematic symbols, and a layout abstraction to place and route. The program in Skill language can automatically complete the creation of all the models in different levels. The SRAM compiler has a friendly user interface. Users can specify the necessary parameters and then get all the results. The SRAM compiler can be easily integrated into Cadence and other CAD frameworks." @default.
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- W2097323304 date "2003-06-25" @default.
- W2097323304 modified "2023-09-27" @default.
- W2097323304 title "A flexible embedded SRAM compiler" @default.
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- W2097323304 doi "https://doi.org/10.1109/delta.2002.994676" @default.
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