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- W2097446125 abstract "This paper proposes new SOI circuit strategies for simultaneous reduction of standby gate and sub-threshold leakages. Various enhanced MTCMOS design alternatives are analyzed. A new method for assigning the V/sub TH/ and sizes of header and footer transistors is proposed, and stacking of headers/footers is analyzed. The optimum stacking height and tapering/sizing ratio under various design constraints are determined. Our strategies reduce MTCMOS standby leakage further by as much as 20/spl times/ and reduce virtual supply noise by 15%." @default.
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- W2097446125 date "2003-01-01" @default.
- W2097446125 modified "2023-09-25" @default.
- W2097446125 title "New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology" @default.
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- W2097446125 doi "https://doi.org/10.1145/871506.871548" @default.
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