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- W2097534296 abstract "A phase-locked loop (PLL) with two different delay feedback paths is presented. It provides a new approach to minimize the dead zone, jitter accumulation, long settling time and nonidealities on PFD/CP. This PLL utilizes a tunable delay cell to reduce the ripple on the VCO control line and hence the jitter penalty. In addition, a fully differential delay cell for voltage-controlled oscillator (VCO) is introduced to perform a wide locking range and low-jitter performance. The proposed PLL was implemented in 0.35-/spl mu/m 2P4M CMOS standard technology with the core area of 0.1mm. It can be operated from 250MHz to 1.29GHz and consume 38.2mW of power at 1GHz under a 3.3-V supply voltage." @default.
- W2097534296 created "2016-06-24" @default.
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- W2097534296 date "2005-07-27" @default.
- W2097534296 modified "2023-09-27" @default.
- W2097534296 title "A Frequency Synthesizer using Two Different Delay Feedbacks" @default.
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- W2097534296 doi "https://doi.org/10.1109/iscas.2005.1465208" @default.
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