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- W2097660237 abstract "An all-digital built-in jitter measurement (BIJM) circuit is presented in this paper. A frequency divider is taken as a timing amplifier to linearly amplify the input jitter. Subsequently, a vernier ring oscillator (VRO) is used as a time-to-digital converter (TDC) to quantize the jitter information into digital codes. The proposed self-referred architecture with a cycle-controlled delay line doesn't require an external reference clock to measure the jitter of the on-chip signals. Therefore, the BIJM circuit design complexity is greatly reduced by the proposed architecture. The proposed all-digital BIJM is implemented in a 65nm CMOS process, and the input frequency range is 100MHz to 300MHz." @default.
- W2097660237 created "2016-06-24" @default.
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- W2097660237 date "2011-04-01" @default.
- W2097660237 modified "2023-09-24" @default.
- W2097660237 title "An all-digital on-chip jitter measurement circuit in 65nm CMOS technology" @default.
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- W2097660237 doi "https://doi.org/10.1109/vdat.2011.5783605" @default.
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