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• W2097800054 abstract "The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective fault models and test signals generators are still missing. This paper proposes ARPIA, a new simulation-based evolutionary test generator. ARPIA adopts an innovative high-level fault model that enables efficient fault simulation and guarantees good correlation with gate-level results. The approach exploits an evolutionary algorithm to drive the search of effective patterns within the gigantic space of all possible signal sequences. ARPIA operates on register-transfer level VHDL descriptions and generates effective test patterns. Experimental results show that the achieved results are comparable or better than those obtained by high-level similar approaches or even by gate-level ones." @default.
• W2097800054 created "2016-06-24" @default.
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• W2097800054 date "2001-01-01" @default.
• W2097800054 modified "2023-09-27" @default.
• W2097800054 title "ARPIA: A High-Level Evolutionary Test Signal Generator" @default.
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• W2097800054 doi "https://doi.org/10.1007/3-540-45365-2_31" @default.
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