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- W2098032901 abstract "We present a 2.45 GHz fully-differential CMOS power amplifier (PA) with high efficiency and linearity. We have adopted a 0.18 /spl mu/m standard CMOS process with Cu-metal and all components of the 2-stage circuit are integrated into one chip. To improve the linearity, we adopt a new harmonic termination technique at the common source along with the normal harmonic termination at the drain. The harmonic termination at the source suppresses the second harmonic generated at the input C/sub gs/. The amplifier shows 17.5 dB of power gain and 20.5 dBm of P/sub 1dB/ with 37 % of PAE. Linearity measurements from a 2-tone test show that the power amplifier with the second harmonic termination at the source improves a maximum 6 dB of IMD3 and 7 dB of IMD5 over the amplifier with harmonic termination at the drain only. Furthermore, the linearity improvements appear over the entire range of the power level and the linearity remains low below 45 dBc of IMD3 and -57 dBc of IMD5 for an output power backed-off more than 5 dB from P/sub 1dB/." @default.
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- W2098032901 date "2005-08-10" @default.
- W2098032901 modified "2023-09-27" @default.
- W2098032901 title "Differential CMOS linear power amplifier with 2nd harmonic termination at common source node" @default.
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- W2098032901 doi "https://doi.org/10.1109/rfic.2005.1489838" @default.
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