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- W2098066607 abstract "This paper presents a new ADC based on using passive charge sharing SAR ADC in a 2-stage pipeline architecture. The charge domain operation of passive charge sharing ADC poses an inherent limitation on its resolution. The proposed architecture increases the achievable resolution with a low power overhead. Designed and simulated in a 0.18um CMOS process, the 12-bits, 40MS/sec ADC core consumes 7mW from a 1.8V supply." @default.
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- W2098066607 date "2008-11-01" @default.
- W2098066607 modified "2023-10-14" @default.
- W2098066607 title "A two-stage pipelined passive charge-sharing SAR ADC" @default.
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- W2098066607 doi "https://doi.org/10.1109/apccas.2008.4745980" @default.
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