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• W2098622191 abstract "The Broadcom BCM12500 is a high performance system on a chip (SOC) targeted at network centric tasks. The chip consists of two high performance SB-1 MIPS64/sup TM/ CPUs, a shared 512 KB L2 cache, a DDR memory controller, and integrated I/O. All major blocks of the processor are connected together via the ZBbus/sup TM/; a high speed split transaction fully coherent multi processor bus. Three Gigabit Ethernet MACs enable a direct interface to network elements. High-speed system I/O is provided using AMD's Lightning Data Transport (LDT/sup TM/) I/O fabric and a 66 MHz PCI bus. The die measures 14.2 mm by 13.3 mm in a bulk 0.15 /spl mu/m CMOS technology and has a power dissipation of 13 W at 1.2 V and 1 GHz." @default.
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• W2098622191 date "2002-11-13" @default.
• W2098622191 modified "2023-09-27" @default.
• W2098622191 title "A 1 GHz power efficient single chip multiprocessor system for broadband networking applications" @default.
• W2098622191 cites W1485181160 @default.
• W2098622191 doi "https://doi.org/10.1109/vlsic.2001.934209" @default.
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