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- W2099094547 abstract "It is becoming unfeasible to create large high gate count System-on-Chip devices within the short development times being demanded unless existing design methodologies are adapted. The trends continue relentlessly with further demand for reduction of time-to-market device gate count increasing in accordance with Moore's Law and growing consumer expectations for improved cost/functionality in each new generation of products. It is also being widely recognised that reuse and sharing of virtual components (VCs) is becoming fundamental to closing the deep sub-micron design gap for successful System-on-Chip design. Design reuse can increase productivity while also enabling faster more complex IC designs. A recent study warns that companies who do not embrace the use of such commercial IP could quickly find themselves at a strategic disadvantage. The paper describes an approach used within ARM to develop reusable soft IP (intellectual property) designs. Reference is made to PrimeCell designs which are System-on-chip peripherals having bus interfaces based on ARM's Advanced Microcontroller Bus Architecture. Reusable IP designs are targeted for widespread usage, and faster and easier integration in a multiple source IP chip synthesis design flow. Design reuse is considered in a wide context, applying it to the complete design together with associated development environment, test infrastructure and documentation. The emphasis is on reduction of time-to-market in order to bridge the growing process-productivity gap for System-on-Chip devices, by designing for wide usage with independence from semiconductor processes and design tools." @default.
- W2099094547 created "2016-06-24" @default.
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- W2099094547 date "2003-01-20" @default.
- W2099094547 modified "2023-09-23" @default.
- W2099094547 title "Designing for the IP supermarket" @default.
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- W2099094547 doi "https://doi.org/10.1109/viuf.1999.801970" @default.
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