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- W2099108362 abstract "A high-speed 32*32-b parallel multiplier with an improved parallel structure using 0.8- μm CMOS triple-level-metal technology is discussed. A unit adder, a 4-2 compressor, enhances the parallelism of the multiplier array. A 25% reduction in the propagation delay time is achieved by using the compressor. The multiplier contains 27704 transistors with a 2.68-*2.71-mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> die area. The multiplication time is 15 ns at 5 V with a power dissipation of 277 mW at 10-MHz operation. The triple-level-metal interconnection technology reduces the multiplier layout area. Compared with double-level-metal technology, a 27% chip size reduction is achieved." @default.
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- W2099108362 date "1990-04-01" @default.
- W2099108362 modified "2023-09-28" @default.
- W2099108362 title "A 15-ns 32*32-b CMOS multiplier with an improved parallel structure" @default.
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- W2099108362 doi "https://doi.org/10.1109/4.52175" @default.
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