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• W2099161646 abstract "Scan-based DFT is the de-facto industrial practice for testing integrated circuits (ICs). Variations in the scan architecture to improve test metrics have been the primary focus in recent years. In this paper, we propose a new nonscan DFT in which a subset of the circuit flip-flops are made directly loadable from the primary inputs and another subset of flip-flops are made observable at the output via a state compactor. In this architecture, multiple flip-flops may share the same primary input in the loading mode. A load-enable pin is added to distinguish the direct-loading mode from the functional mode. With a modest area overhead, this architecture offers several attractive features, including (1) at-speed testing, which eliminates the need for scan-shifting and would thus capture delay-related defects, (2) low test data volume and test application time, as we no longer need to store all the scan and response data, (3) high coverages, since the low-testability flipflops are made to be loadable and/or observable, and (4) low test power. Experimental results on large ISCAS'89 circuits validate the aforementioned metrics with 10× to 100× reduction in test application time with respect to Illinois Scan." @default.
• W2099161646 created "2016-06-24" @default.
• W2099161646 creator A5006221821 @default.
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• W2099161646 date "2009-01-01" @default.
• W2099161646 modified "2023-10-16" @default.
• W2099161646 title "Kiss the Scan Goodbye: A Non-scan Architecture for High Coverage, Low Test Data Volume and Low Test Application Time" @default.
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• W2099161646 doi "https://doi.org/10.1109/ats.2009.17" @default.
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