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• W2099170293 abstract "A 60-mW MPEG4 video codec has been developed for mobile multimedia applications. This codec supports both the H.263 ITU-T recommendation and the simple profile of MPEG4 committee draft version 1 released in November 1997. It is composed of a 16-bit reduced instruction set computer processor and several dedicated hardware engines so as to satisfy both power efficiency and programmability. It performs 10 frames/s of encoding and decoding with quarter-common intermediate format at 30 MHz. Several innovative low-power techniques were employed in both architectural and circuit levels, and the final power dissipation is 60 mW at 30 MHz, which is only 30% of the power dissipation for a conventional CMOS design. The chip was fabricated in a 0.3-/spl mu/m CMOS with double-well and triple-metal technology. It contains 3 million transistors, including a 52-kB on-chip SRAM. Internal supply voltages of 2.5 and 1.75 V are generated by on-chip dc-dc converters from 3.3-V external supply voltage." @default.
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• W2099170293 date "1998-01-01" @default.
• W2099170293 modified "2023-10-01" @default.
• W2099170293 title "A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme" @default.
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• W2099170293 doi "https://doi.org/10.1109/4.726575" @default.
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