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- W2099215665 abstract "Load instructions usually have long execution latency in a deep processor pipeline, and have significant impact on overall performance. Therefore, how to hide the load latency becomes a serious problem in processor design. The latency of memory load can be separated into two parts: cache-miss latency and load-to-use latency. Previous work which tried to hide the load latency in a deep processor pipeline has some limitations. In this paper, we propose a hardware-based method, called early load, to hide the load-to-use latency with little hardware overhead. Early load scheme allows load instructions to load data from the cache system before it enters the execution stage. In the meantime, a detection method makes sure the correctness of the early operation before the load instruction enters the execution stage. Our experimental results showed that our approach can achieve 11.64% performance improvement in Dhrystone benchmark and 4.97% in average for MiBench benchmark suite." @default.
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- W2099215665 date "2008-08-01" @default.
- W2099215665 modified "2023-09-25" @default.
- W2099215665 title "Early load: Hiding load latency in deep pipeline processor" @default.
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- W2099215665 doi "https://doi.org/10.1109/apcsac.2008.4625440" @default.
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